A semiconductor memory unit is a collection of storage cells together with associated circuits needed to transfer information (data) in and out of the device. Two basic types of semiconductor memories are nonvolatile, of which a ROM (read-only memory) is typical, and volatile, of which a RAM (random access memory) is typical.
In ROM, data is permanently or semi-permanently stored and can be read at any time. In a ROM in which the data are permanently stored, data is either manufactured into the device or programmed into the device and cannot be altered. In a ROM in which the data are semi-permanently stored, the data can be altered by special methods, such as by exposure to ultraviolet light or by electrical means. ROM write operations require special methods.
RAM is memory that has both read and write capabilities. RAM circuits generally come in two forms. The first form of RAM is known as a static RAM circuit (xe2x80x9cSRAMxe2x80x9d). A primary characteristic of an SRAM circuit is that the circuit has latches in which data may be indefinitely retained, provided power is connected to the circuit. The second form of RAM is known as a dynamic RAM circuit (xe2x80x9cDRAMxe2x80x9d). A primary characteristic of a DRAM circuit is that the circuit uses charge storing elements, such as capacitors, to retain the stored data in the storage locations, and the circuit must periodically refresh its data to retain it.
A conventional computer or processor has internal (or main) RAM. The computer can manipulate data only when it is in the main memory. Every program executed and file accessed must be copied from a storage device into main memory. After program or file data manipulation or utilization is complete, the RAM bits that comprise that data may be erased or overwritten by another program or file. Thus, the amount of main memory on a computer is important, as it determines how many programs can be executed at one time and how much data can be readily available to a program.
One restraint on computer memory (ROM or RAM) capacity is the physical dimensions of a disk or chip. RAM capacity is limited also by power, heat, and manufacturing limitation constraints. Because a single chip may store millions of bits of data, simplification of chip circuitry for processing bits in and out of ROM and RAM is highly desired.
The communication between a memory and its environment is achieved through data input and/or output lines, address selection lines, and control lines that specify the direction of transfer. In a conventional memory circuit, data is stored in a plurality of storage locations arranged as an array (or a group of sub-arrays) of memory cells. Each storage location is identified by an address, which might include both a row identifier and a column identifier. In conventional memory circuits, internal data lines transfer the data to the storage locations during a write cycle and transfer the data from the storage locations during a read cycle.
A simplified overview of a prior art read cycle will now be described. Three generalized components of a prior art read cycle are represented in FIG. 1. Memory cell 10 is one of the thousands or millions of storage locations within a memory 12. While each storage location may accommodate one or more bits, to simplify the present discussion, it will be assumed that memory cell 10 has only one bit. For purposes of this discussion, it may be assumed that the proper addressing and control signals have been activated for accessing the contents of memory cell 10.
As is well known by those skilled in the art, bit data processing must occur within predetermined timing specifications. The rate of bit processing not only affects the overall speed of the processor, but bits sequentially occupy the same processing components and lines. Thus, it is desirable to have fast bit data processing speeds. Typically, however, the magnitude of the charge stored for representing a bit in memory storage is too low to quickly drive output circuits. Consequently, circuitry has been incorporated into memory chips to increase the speed of data read cycles. To ameliorate the aforementioned processing speed and power constraints, read processing circuitry 14 has been incorporated in memory chips for processing bit data to external circuitry 18. Generally, such circuitry has been devised for quickly detecting the status of the bit, i.e., xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d, and for responsively providing a bit status data signal that can quickly and accurately be detected by the external circuitry.
Prior art read processing circuitry 14 has included transposing the bit data as represented in the memory cell bank to a format that is more suitable for processing. One such format represents data (0 or 1) on dual data lines, A and B, as follows:
In this example, the signals on lines A and B are processed in parallel from a data line to a latch. The latch receives the signals on lines A and B at latch inputs and responsively provides output signals on output lines A and B. The signals on the output lines are preferably driven HIGH by the system power source and driven LOW by system ground, thus providing relatively strong output signals to the external circuitry.
In the dual data line embodiment discussed above, it has long been known in the art that there are advantages to xe2x80x9cequalizingxe2x80x9d the data lines and latch nodes using data line equalization circuitry and latch node equalization circuitry. Equalization ensures that data lines begin at the same potential, thereby preconditioning the lines for the application of opposite (e.g., high or low) bit representation voltages. Thus, received data bit signals will be detected quickly and accurately. It has been recognized in the prior art that these and other advantages are realized by equalizing the data latch input nodes, which receive on the xe2x80x9cAxe2x80x9d line and the xe2x80x9cBxe2x80x9d line high and low data bit signals and responsively provide HIGH and LOW output signals.
In the prior art, the data latch nodes and/or the data lines are equilibrated by pre-charging both the latch nodes and the data lines to the same voltage magnitude. Typically, the latch nodes and data lines are both temporarily connected to a voltage source, such as the chip power supply. In this example, the data lines and latch nodes are charged to VCC and then isolated from the chip power supply. The equilibrated data lines (xe2x80x9cAxe2x80x9d and xe2x80x9cBxe2x80x9d) receive the bit data signals, which are thereafter (in accord with processor timing specifications) provided to the equilibrated data latch nodes.
An improvement to the prior art equilibrating technique described above is disclosed in U.S. provisional patent application No. 60/185,300 (Two Phase Charge-Sharing Data Latch for Memory Circuit), filed Feb. 28, 2000, hereby incorporated herein by reference. In the data read circuit disclosed therein, the data latch nodes are equilibrated, but not through a direct connection to a power source. Rather, each latch node is equilibrated by sharing the charge of its respective pre-charged data line. Specifically, the data lines, while isolated from the latch nodes, are equilibrated to VCC as discussed above. Prior to the application of bit data on the data lines, a switch is activated so that each latch node is electrically connected to its respective data line. The capacitance of each latch node relative to its respective data line provides a charge sharing scheme through which the latch nodes are equilibrated to VCC.
In another, more sophisticated data line and latch node design, the data lines and latch nodes are pre-charged to a voltage magnitude other than VCC, referred to herein as VCCI. That is, the external voltage source magnitude and the internal voltage source magnitude are not equivalent. In this variation, VCC and VCCI are preferably generated from a voltage down converter supplied by a supply voltage VCCX. For outputting bit data, however, the latch nodes are still driven to VCC and VSS. Thus, this design includes an internal level shift between VCC and VCCI. One advantage of this design is that the equilibrated data lines do not encounter large voltage swings, such as from VCC to VSS. Rather one data line is driven from VCCI to VSS while the other data line remains at VCCI. Such a design also has the advantage of lower power consumption.
Prior art read circuits that pre-charge the latch nodes to VCCI employ a voltage source selectively connectable to the latch nodes for driving the latch nodes to VCCI. The latch power supply voltage in these prior art circuits is the same as the pre-charge voltage and an additional circuit is added between the latch outputs and the external circuits to level shift the signal voltage up to the power supply level of the external circuits. Heretofore, a data read circuit in which the data latch nodes are pre-charged to an intermediary voltage (such as VCCI) has not been designed without such a voltage source directly connected to the latch nodes or without any specific level shifting circuitry.
Thus, there is a need in the art for a memory data latch that does not require that the latch nodes be explicitly pre-charged from a voltage source and that does not require circuitry to shift the signal voltage level from an internal voltage to the voltage used by external circuitry.
The present invention provides a dynamic data amplifier latch that equalizes the latch nodes and level shifts between the memory""s internal voltage and the external circuitry voltage without the addition of any additional circuitry to perform these functions. Another aspect of the present invention is that the internal data latch nodes are equalized and level shifted before a data read cycle by selectively removing their isolation from data read lines upstream in the data flow, which data read lines have been equalized and preferably pre-charged to a lower voltage than the power supply voltage for the latch. The data read lines are of a higher capacitance relative to the capacitance of the latch nodes. When a channel between the data lines and the latch nodes opens, the pre-charge is distributed through both the latch nodes and data lines. Because the capacitance of the data lines is greater than that of the latch nodes, the magnitude of the shared pre-charge does not drop significantly, equalizing the latch nodes. Upon receipt of data signals of relatively lower magnitude, the previously equalized latch subsequently amplifies and latches providing output data signals of a higher magnitude.
Preferably, a first switching device is provided for selectively connecting the data lines and data latch nodes, i.e., establishing a channel therebetween. While the switch is closed and the data lines are isolated from the data latch nodes, the data lines are pre-charged to the memory""s internal operating voltage level as the latch nodes continue to latch the output data from the previous memory read cycle at the higher operating voltage of the circuitry external to the memory. At the beginning of the next read cycle, the switch opens and the latch nodes are equalized to the memory""s internal power supply voltage and level shifted down from the higher power supply voltage of the circuitry external to the memory by sharing the pre-charge of the equalized data lines. In one embodiment, a pair of transistors is used for the switching device, one transistor for each latch node/data line pair.
A precharge and equalizing circuit is preferably provided and connected to the data lines for precharging and equalizing the data lines to a predetermined voltage level. Preferably, the precharge and equalizing circuit is activated while the switching device is off, thereby isolating the data lines from the latch nodes. When the precharge and equalizing circuit is deactivated and isolated from the data lines, the switching device connects each data line to its corresponding latch node. When the data bit voltage signals are later received from the data lines, a HIGH voltage signal is latched on one latch node and a LOW voltage signal is latched on the other latch node. The magnitude of the HIGH voltage signal is greater than the magnitude of the equilibration voltage.